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RM0008
Table 86.
Flexible static memory controller (FSMC)
Memory mapping and timing registers
Start address
End address
FSMC Bank
Memory space
Timing register
0x9C00 0000
0x9800 0000
0x9000 0000
0x8800 0000
0x9FFF FFFF
0x9BFF FFFF Bank 4 - PC card
0x93FF FFFF
0x8BFF FFFF
I/O
Attribute
Common
Attribute
FSMC_PIO4 (0xB0)
FSMC_PATT4 (0xAC)
FSMC_PMEM4 (0xA8)
FSMC_PATT3 (0x8C)
Bank 3 - NAND Flash
0x8000 0000
0x7800 0000
0x83FF FFFF
0x7BFF FFFF
Common
Attribute
FSMC_PMEM3 (0x88)
FSMC_PATT2 (0x6C)
Bank 2- NAND Flash
0x7000 0000
0x73FF FFFF
Common
FSMC_PMEM2 (0x68)
For NAND Flash memory, the common and attribute memory spaces are subdivided into
three sections (see in Table 87 below) located in the lower 256 Kbytes:
●
●
●
Data section (first 64 Kbytes in the common/attribute memory space)
Command section (second 64 Kbytes in the common / attribute memory space)
Address section (next 128 Kbytes in the common / attribute memory space)
Table 87.
NAND bank selections
Section name
Address section
Command section
Data section
1X
01
00
HADDR[17:16]
Address range
0x020000-0x03FFFF
0x010000-0x01FFFF
0x000000-0x0FFFF
The application software uses the 3 sections to access the NAND Flash memory:
●
●
●
To send a command to NAND Flash memory : the software must write the command
value to any memory location in the command section.
To specify the NAND Flash address that must be read or written : the software must
write the address value to any memory location in the address section. Since an
address can be 4 or 5 bytes long (depending on the actual memory size), several
consecutive writes to the address section are needed to specify the full address.
To read or write data : the software reads or writes the data value from or to any
memory location in the data section.
Since the NAND Flash memory automatically increments addresses, there is no need to
increment the address of the data section to access consecutive memory locations.
Doc ID 13902 Rev 9
413/995
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